Turning to FIG. 1, a diagram of the conventional routing model for packet switching networks can be seen. In this model, a core network 112 communicates over the internet 102 through core routers 104-1 to 104-N. The core network 112 generally communicates with the core routers 104-1 to 104-N with intermediate switches 106-1 to 106-M; usually, two intermediate switches (i.e., 106-1 and 106-2) communicate with a core router (i.e. 104-1). The intermediate switches 106-1 to 106-M are then each able to communicate with each aggregate switch 108-1 to 108-K, which are each in communication with TOR switches 110-1 to 110-L. These TOR switches 110-1 to 110-L can then each be in communication with several (i.e., 20) servers.
Of interest here are the TOR switches 110-1 to 110-K, and a diagram of an example of a TOR switch (which is labeled 110) can be seen in FIGS. 2 and 3. Usually, as part of a data center, servers are held in a “rack” and the TOR switch 110 is located within the rack (typically at the top) so as to operate as a forwarding switch. As shown, this TOR switch 110 is generally comprised of a processor 202, switching circuit 204, a ternary context-addressable memory (TCAM) 210, and input/output (I/O) circuitry (which generally includes physical layer (PHY) circuit 206-1 to 206-J and ports 208-1 to 208-P), and the switching circuit 204 generally comprises an input queue 302, a parser 304, a search engine 306, processor interface 308, action circuit 310, and output queue 312. In operation, data packets (which each generally have a header and a body) are received through the ports 208-1 top 208-P and PHY circuits 206-1 to 206-J. These packets are stored in the input queue 302 (which is typically a first-in-first-out (FIFO) circuit), and the parser 304 is able to extract the header from these queued packets. Using the extracted headers, the search engine 210 is able to search the TCAM 210 to determine a rule associated with the header, where each rule is associated with an action. Once identified, the action circuit modifies the packet (usually the header) in accordance with the action associated identified rule. The modified packet is then placed in the output queue 312 (which is typically a FIFO circuit) so as to be transmitted.
Specifically and as detailed above, the search engine 306 performs packet lookups using the TCAM 210, which is a high speed memory that allow for matches over a large database of ternary packet-forwarding rules (i.e., Access Control Lists, Destination IP rules, and NetFlow rules). TCAM 210, though, consume several multiples of power and area compared to other memory types (such as SRAM or embedded DRAM) making it difficult to embed large TCAMs on-chip. As a result, TOR switches 110-1 to 110-L suffer from in penalties of power and area, as well as limited flexibility because the TOR switches 110-1 to 110-L set the forwarding rules. Therefore, there is a need for an improved TOR switch with a lower cost and higher flexibility.
Some other conventional systems are: U.S. Pat. No. 7,028,098; U.S. Pat. No. 7,234,019; U.S. Pat. No. 7,382,787; U.S. Patent Pre-Grant Publ. No. 2005/0262294; U.S. Patent Pre-Grant Publ. No. 2011/0161580; and Mysore et al., “PortLand: A Scalable Fault-Tolerant layer 2 Data Center Network Fabric,” SIGCOMM 2009, Aug. 17-21, 2009.